Exploring FPGA Switch-Blocks without Explicit Pattern Listing

Increased lower metal resistance makes physical aspects of Field-Programmable Gate Array (FPGA) switch-blocks more relevant than before. The need to navigate a design space where each individual switch can have significant impact on the FPGA’s performance in turn automated switch-pattern exploration techniques increasingly appealing. However, most existing fundamental limitation—they use CAD tools as black box evaluate explicitly listed switch-patterns. Given time needed route modern circuit single architecture, number switch-patterns that be tested quickly becomes negligible compared size space. This paper presents technique removes this limitation by making entire visible router and letting it choose switches added pattern, based requirements circuits being routed. key preventing from selecting arbitrary would render final pattern excessively large is apply same negotiation principle used remove congestion, just opposite direction, make signals reach consensus which are worthy included switch-pattern.